`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineers: Brentton Garber, Georgii Tkachuk
// 
// Create Date: 17:28:56 05/01/2013 
// Design Name: ALU
// Module Name: ALU
// Project Name: Lab 3
// Target Devices: Xilinx Spartan6 XC6LX16-CS324 
// Tool versions: Xilinx ISE 14.2 
// Description: Computes the sum, multiplication, and comparison of the values in the reg set,
//
// Revision: 1
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
module ALU(
	input CMP,
	input SUM,
	input MUL,
	input [3:0]rega,
	input [3:0]regb,
	output reg [7:0]result);

// Whenever an input is changed
always @(*) begin
	case ({MUL,SUM,CMP})
		// if there is no operation, write 11111111 to the output
		3'b000: result = 8'b1111_1111;
		// if MUL is 1, multiply values
		3'b100: result = rega*regb;
		// if SUM is 1, add values
		3'b010: result = rega + regb;
		// if CMP is 1, compare values
		3'b001: 
		begin
			if(rega == regb)
				result = 8'b1;
			else 
				result = 8'b0;
		end
		// Default, return all 1s'
		default:	result = 8'b1111_1111;
	endcase
end 
endmodule
